FT-NMR spectroscopy is acutely dependent upon modern real time data acquisition methods. A computer based system is dictated by the multiple requirements for control of the spin excitation process, monitoring of system operating parameters, response to operator intervention, acquisition of time domain data, time averaging of such data, Fourier transformation operations on the data and subsequent data reduction. Accordingly, considerable burden is placed upon any single processing unit to accommodate all of these functions while maintaining the necessary data acquisition rate with required synchrony.
The most recent prior art approach to this problem segregates functions in a multiple processor system linked by a common bus and sharing access to a common memory. One of such processers is a special purpose acquisition processor dedicated to commanding the pulse sequence of the spectrometer, monitoring the spectrometer parameters, commanding data conversion by the analog-to-digital converter, hereafter ADC, and performing time averaging operations on the acquired data. The general purpose processor functions as a host, interpreting keyboard commands for general operating purposes and serving to operate upon frequency domain data for desired data reduction, performing Fourier transformation of the time averaged data to the frequency domain, and performing display and output operation. The various functions are accommodated by linked but otherwise independent processors. To assure synchrony in the acquisition of time domain data and to satisfy the various demands upon it, the system is structured upon a priority interrupt organization. This system is especially characterized in the manner in which the acquisition processor, by its structural coupling with the spectrometer, avoids overlap between spectrometer control and data acquisition functions. This is accomplished in part by stacking a series of commands in an advancing sequence buffer. (The advancing sequence buffer comprises a plurality of serially communicating registers for advancing a sequence of digital words toward an output buffer. Thus the advancing sequence buffer is known as a "first in-first out" or FIFO buffer.) Each command word comprises an operation portion and a persistence time portion. The internal FIFO advance signal is then controlled by a timing means which decodes the persistence time portion and maintains the currently active command word at the output register of the FIFO for the specified persistence time. At the termination of the currently active persistence interval, the FIFO content is then advanced. This technique permits the acquisition processor to accommodate certain of its nonsynchronous functions during the autonomous operation of the FIFO. More important, the synchrony of commands to the spectrometer is carefully preserved during the operational discharge of FIFO content. This apparatus is the subject of U.S. Pat. No. 4,191,919 commonly assigned with the present invention.
The above-referenced apparatus preserves synchrony and frees the acquisition processor only for the period jointly defined by the number of command words accommodated by the FIFO and by the respective persistence times of such words. Because the number of transient waveforms may be large, the number of samples defining each waveform also quite large, and the number of excitation and auxiliary commands indefinite, the above-described prior art apparatus requires frequent servicing of the FIFO by the acquisition processor. Consequently, the interrupt rate at the acquisition processor, although reduced (over a conventional priority interrupt organized system), may still be quite high and require substantial penalty in the software for accommodating the varies levels of priority required.
Sequence buffers which operate on a first in-first out principle have been known in the computer art for many years for processing serial word strings for input-output operations. Such applications have been addressed to such aspects as matching disparate information processing rates of the digital processor and the communicating peripheral device for strings of arbitrary length.
Shift registers are another class of apparatus in which a number of parallel bits are subject to serial advance or retard. Shift registers are also known in a form wherein the output is fed back to the input of the register to sequentially process the individual bits of a digital word. These structures are employed for parallel to serial transformation, arithmetic operation or single bit string manipulation in the prior art.